Modeling of Electromigration Induced Failure Mechanisms in Semiconductor Devices

F. Cacho, V. Fiori, C. Chappaz, C. Tavernier, and H. Jaouen
STMicroelectronics, Crolles, France

In advanced semiconductor devices, most of the reliability issues in interconnects occur at a local scale. More precisely, the voiding phenomenon in copper lines is one of the key issues. Hence, a better understanding of the mechanisms governing electromigration would enable the development of more accurate predictive models.

A model of vacancy migration is proposed. The thermal, stress and concentration gradients, and the forces driven by the electrical current are considered.

After reviewing some basic elementary behaviors, such as the Blech length and the local vacancy accumulation at the cathode in a two dimensional model, a more realistic configuration is studied thanks to a three dimensional copper line model.