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Flip-chip (FC) is one of the advanced forms of semiconductor device packaging that is widely used in today's semiconductor packages for its capability to minimize packaging size while enhancing electrical interconnection density and transmission performance. In FC devices, the active side of the chip is placed face down and the chip is bonded directly to the substrate or other carrier via bumps. Due to self-heating or environmental factors, the devices suffer repeated temperature changes during operation, which affects their lifetime. Therefore, the structural reliability of FC devices under temperature cycling conditions is one of the key concerns in package design and test phases, which can be predicted and evaluated by simulation.

In this model, the stress distribution in the chip, bumps, underfill and other regions as well as the overall warpage are analyzed for a FC device during thermal cycling test. The viscoplasticity of solder bumps is considered and the accumulation of viscoplastic strain in solder bumps is calculated. Based on these results, the damage and failure of package structures can be further studied, for example, the thermal fatigue of bumps.